AXI4-Stream Video Interface - 1.1 English

Video Scene Change Detection LogiCORE IP Product Guide (PG322)
Document ID
PG322
Release Date
2023-11-10
Version
1.1 English

The Video Scene Change Detection IP has AXI4-Stream video input and output interfaces named s_axis_video and m_axis_video respectively, when the stream mode is enabled.

Both video streaming interfaces follow the interface specification as defined in the Video IP chapter of the Vivado Design Suite: AXI Reference Guide (UG1037). The video AXI4-Stream interface can be single, dual, or quad pixels per clock and can support 8, 10, 12, or 16 bits per component. The streaming interface configuration (samples per clock and bits per component) is chosen at the IP level and applies to all instances of the AXI4-Stream interface.

The following tables explain the pixel mapping of an AXI4-Stream interface with two pixels per clock and 10 bits per component configuration for all supported video color formats:

Table 1. Dual Pixels Per Clock, 10 Bits Per Component Mapping for RGB
69:60 59:50 49:40 39:30 29:20 19:10 9:0
Zero padding R1 B1 G1 R0 B0 G0
Table 2. Dual Pixels Per Clock, 10 Bits Per Component Mapping for YUV 4:4:4
69:60 59:50 49:40 39:30 29:20 19:10 9:0
Zero padding V1 U1 Y1 V0 U0 Y0
Table 3. Dual Pixels Per Clock, 10 Bits Per Component Mapping for YUV 4:2:2
69:60 59:50 49:40 39:30 29:20 19:10 9:0
Zero padding Zero padding Zero padding V0 Y1 U0 Y0

The following table shows the interface signals for input and output AXI4-Stream video streaming interfaces.

Table 4. AXI4-Stream Interface Signals
Signal Name I/O Width Description
s_axis_tdata I floor(((3× bits_per_component× pixels_per_clock) + 7) / 8) × 8 Input Data
s_axis_tready O 1 Input Ready
s_axis_tvalid I 1 Input Valid
s_axis_tdest I 1 Input Data Routing Identifier
s_axis_tkeep I (s_axis_video_tdata width) / 8 Input byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream.
s_axis_tlast I 1 Input End of Line
s_axis_tstrb I (s_axis_video_tdata width) / 8 Input byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
s_axis_tuser I 1 Input Start of Frame
m_axis_tdata O floor(((3 × bits_per_component× pixels_per_clock) + 7) / 8) × 8 Output Data
m_axis_tdest O 1 Output Data Routing Identifier
m_axis_tid O 1 Output Data Stream Identifier
m_axis_tkeep O (m_axis_video_tdata width) / 8 Output byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream.
m_axis_tlast O 1 Output End of Line
m_axis_tready I 1 Output Ready
m_axis_tstrb O (m_axis_video_tdata width) / 8 Output byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
m_axis_tuser O 1 Output Start of Frame
m_axis_tvalid O 1 Output Valid
  1. All video streaming interfaces run at the IP core clock speed, ap_clk.
  2. For default values required to drive the AXI4-Stream interface signals that are not present in upstream or downstream connected IPs, see the IP Using AXI4-Stream Video Protocol section of Vivado Design Suite: AXI Reference Guide (UG1037).