The Video Scene Change Detection IP has ap_rst_n
pin as a hardware reset option. No software reset option
is available. The external reset pulse needs to be held for 16 or more ap_clk
cycles to reset the core. The ap_rst_n
signal is synchronous to the ap_clk
clock domain. The ap_rst_n
signal resets the entire core including the AXI4-Lite, memory mapped AXI4,
and AXI4-Stream interfaces.