Summary - 3.2 English

HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235)
Document ID
PG235
Release Date
2024-12-11
Version
3.2 English

The HDMI 1.4/2.0 TX Subsystem allows users to customize the example design based on their system requirements. The following table shows a summary of the hardware required for each targeted board, supported processors, topologies, and the corresponding AMD Vitis™ software platform import example options.

Table 1. Example Design Support Summary
Development Boards Additional Hardware Processor Topology Vitis Import Example
KC705/KCU105/VCU118 1 inrevium TB-FMCH-HDMI4K FMC mezzanine card MicroBlaze™ ™ Pass-through Passthrough_Microblaze
TX Only

TxOnly_Microblaze
ZC706 A9 Pass-through Passthrough_A9
TX Only TxOnly_A9
ZCU102 2 /ZCU104/ZCU106 - A53 Pass-through Passthrough_A53
TX Only TxOnly_A53
Pass-Through Repeater_A53 3
Pass-Through + I2S Audio (ZCU102 Only) Passthrough_Audio_I2S_A53
R5 Pass-Through Passthrough_R5
TX Only TxOnly_R5
VCK190/VMK180   A72 Pass-Through Passthrough_A72
  1. For VCU118 board, no dedicated on-board GT reference clocks are available to support the HDMI Transmitter and NI-DRU on the HDMI Receiver simultaneously due to board design limitations. Therefore, if Pass-through topology is selected for the VCU118 board, NI-DRU is disabled.
  2. The HDMI + I2S-PMOD Audio can be generated only using the configurations in the following table.
  3. A dedicated repeater application is added to demonstrate repeater functionality. Note the following:
    • The Repeater feature has been removed from standard pass-through application for all supported processors.
    • This application passes repeater compliance tests (CTS) on SL8800 running on a ZCU102 A53 processor.
    • The same application can also be used for other applications.
    • You must increase the BRAM size from 512K to 1M in hardware IP integrator to run repeater function on the MicroBlaze™ processor. This is because that the repeater functionality is more complex and requires more resources.
  4. In any HDMI design where HDMI RX sends data to HDMI TX without a forwarded clock, it needs to use frame buffer to keep HDMI TX core from overflowing.
  5. The example designs supports only up to 8 Channel Audio.
Table 2. HDMI + I2S-PMOD Audio Configuration
Description Value
Board ZCU102 Revision 1.x
Video Interface AXI4-Stream
Include HDCP 1.4 Encryption Disabled
Include HDCP 2.3 Encryption Disabled
Video over AXIS compliant NTSC/PAL Support Disabled
Video over AXIS compliant YUV420 Support Disabled
Max bits per component 8
Number of pixels per clock on Video Interface 2
Design Topology Pass-Through + I2S Audio
Axilite Frequency 100
TX PLL Type QPLL0/1
RX PLL Type CPLL
Include NIDRU Enabled

This chapter covers the design considerations of a High-Definition Multimedia Interface (HDMI™) 2.0 implementation using the performance features of these AMD subsystems and IP:

  • HDMI 1.4/2.0 with HDCP 1.4/2.3 Transmitter Subsystem
  • HDMI 1.4/2.0 with HDCP 1.4/2.3 Receiver Subsystem (For Pass-through topology only)
  • Video PHY Controller /HDMI GT Subsystem

The design features the transmit-only and the pass-through operation modes for the HDMI solution. In the transmit-only mode, the design displays a color bar pattern from the LogiCORE IP Test Pattern Generator (TPG) core. In the pass-through mode, an external HDMI source is used to send video data over the HDMI design. The reference design demonstrates the use of the High-bandwidth Digital Content Protection System (HDCP) Revision 1.4/2.3 capability of the HDMI solution. HDCP is used to securely send audiovisual data from an HDCP protected transmitter to HDCP protected downstream receivers. Typically, HDCP 2.3 is used to encrypt content at Ultra High Definition (UHD) while HDCP 1.4 is used as a legacy encryption scheme for lower resolutions.