Native Video Input Interface - 3.2 English

HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235)

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3.2 English

The primary interface for user image data has been modeled on the industry standard for display timing controller signals. The port list consists of video timing information encoded in a vertical and horizontal sync pulse and data valid indicator.

Vertical timing is framed using the vertical sync pulse which indicates the end of frame N - 1 and the beginning of frame N. The vertical back porch is defined as the number of horizontal sync pulses between the end of the vertical sync pulse and the first line containing active pixel data. The vertical front porch is defined as the number of horizontal sync pulses between the last line of active pixel data and the start of the vertical sync pulse. When combined with the vertical back porch and the vertical sync pulse width, these parameters form what is commonly known as the vertical blanking interval.

The following figure shows the typical signaling of a full frame of data. 

Figure 1. Native Interface Vertical Timing

Similarly, the horizontal timing information is defined by a front porch, back porch, and pulse width. The porch values are defined as the number of clocks between the horizontal sync pulse and the start or end of active data. Pixel data is only accepted into the image data interface when the data valid flag is active-High. The following figure is an enlarged version of the previous figure, giving more details on a single scan line. The horizontal sync pulse should be used as a line advance signal. Use the rising edge of this signal to increment the line count.

Figure 2. Native Interface Horizontal Timing

In the two-dimensional image plane, these control signals frame a rectangular region of active pixel data within the total frame size. This relationship of the total frame size to the active frame size is shown in the following figure.

Figure 3. Active Image Data

Note: Native Video Pixel mapping for RGB/YCbCr44/YCbCr422 is same as AXI4-Stream Video format. Refer to AXI4-Stream Video Input Stream Interface for more details on pixel mapping.
Note: HDMI 1.4/2.0 TX Subsystem supports both negative/positive polarities for HSync and VSync Video signals.

The following figures shows timing diagrams for the dual and quad pixel interface options.

Figure 4. Native Video Interface: Dual Pixel Timing

In Native Video or Native Video (Vectored DE) interface, the IP supports YCbCr 4:2:0. However, you must process YCbCr 4:2:0 Pixel Encoding. See Section 7 in the HDMI 2.0b Specification ( following figures illustrates the YCbCr 4:2:0 Pixel Encoding for Dual and Quad Pixel interface.

Figure 5. YCbCr 420 Native HDMI Video Interface (Dual Pixel per Clock)

Figure 6. YCbCr 420 Native HDMI Video Interface (Four Pixels per Clock)