Running the Reference Design (R5 on Zynq UltraScale+ Devices)

Running the Reference Design (R5 on Zynq UltraScale+ Devices) - 3.2 English

HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235)

Document ID

PG235

Release Date

2023-10-18

Version

3.2 English

Launch the Xilinx System Debugger by selecting Start > All Programs > Xilinx Design Tools > Vivado <version> > Vivado <version> Tcl Shell.
In the AMD command shell window, change to the Example Design Project directory.
```
Vivado% cd ./<IP instance name>_ex
```
Invoke Xilinx System Debugger (xsdb).
```
Vivado% xsdb
```
Establish connections to debug targets.
```
xsdb% connect
```

List all available JTAG targets.

xsdb% targets
  1 PS TAP
  2 PMU
  3 PL
  4 PSU
  5 RPU (Reset)
  6 *Cortex-R5 #0 (RPU Reset)
  7 Cortex-R5 #1 (RPU Reset)
  8 APU
  9 Cortex-A53 #0 (Running)
  10 Cortex-A53 #1 (Power On Reset)
  11 Cortex-A53 #2 (Power On Reset)
  12 Cortex-A53 #3 (Power On Reset)

Note: The target number for the PSU, PL, RPU, and Cortex-R5F might be different. Run the targets and ensure they are using the correct target number.

Download the bitstream to the FPGA.

xsdb% source <Vitis Install folder>/scripts/vitis/util/zynqmp_utils.tcl
xsdb% targets -set 4 (PSU)
xsdb% rst -system
xsdb% after 3000
xsdb% target -set 3 (PL)
xsdb% fpga -file ./<IP instance name>_ex.runs/impl_1/exdes_wrapper.bit

Set the target processor.

xsdb% target -set 9 (Cortex-A53 #0)
xsdb% rst -processor
xsdb% dow ./<vitis_workspace>/<platform_name>/export/<platform_name>/sw/<platform_name>/boot/fsbl.elf
xsdb% after 1000
xsdb% con
xsdb% after 1000
xsdb% stop
xsdb% after 1000

Download the software .elf to the FPGA.

xsdb% target -set 6 (Cortex-R5 #0)
xsdb% rst -processor
xsdb% dow ./<vitis_workspace>/<application_name>_1/Debug/<application_name>_1.elf

Run the software.
```
xsdb% con
```
Exit the XSDB command prompt.
```
xsdb% exit
```