Clock frequency constraints are
required for the s_axi_cpu_aclk, s_axis_video_aclk, s_axis_audio_aclk, link_clk, and video_clk.
create_clock -name s_axi_cpu_aclk -period 10.0 [get_ports s_axi_cpu_aclk]
create_clock -name s_axis_audio_aclk -period 10.0 [get_ports s_axis_audio_aclk]
create_clock -name link_clk -period 13.468 [get_ports link_clk]
create_clock -name video_clk -period 6.734 [get_ports video_clk]
create_clock -name s_axis_video_aclk -period 5.0 [get_ports s_axis_video_aclk]When using this subsystem in the
Vivado Design Suite flow with Video PHY Controller
/HDMI
GT Subsystem modules, link_clk, and video_clk are generated from the Video PHY Controller
/HDMI GT
Subsystem. Therefore, the clock constraints are set to the Video PHY Controller
/HDMI
GT Subsystem constraints instead of these generated clocks. See Clocking in the
Video PHY Controller LogiCORE IP Product Guide
(PG230)
/
HDMI GT Controller LogiCORE IP Product Guide
(PG334)
for more
information.
The s_axi_cpu_aclk, s_axis_video_aclk, and
s_axis_audio_aclk constraints are generated at
system level, for example by using a clock wizard.