Running the Reference Design (A9 on Zynq Ultrascale+ Devices)

Running the Reference Design (A9 on Zynq Ultrascale+ Devices) - 3.2 English

HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235)

Document ID

PG235

Release Date

2023-10-18

Version

3.2 English

Launch the Xilinx System Debugger by selecting Start > All Programs > Xilinx Design Tools > Vivado <version> > Vivado <version> Tcl Shell.
In the AMD command shell window, change to the Example Design Project directory.
```
Vivado% cd ./<IP instance name>_ex
```
Invoke Xilinx System Debugger (xsdb).
```
Vivado% xsdb
```
Establish connections to debug targets.
```
xsdb% connect
```

List all available JTAG targets.

xsdb% targets
  1 APU
  2* ARM Cortex-A9 MPCore #0 (Suspended)
  3 ARM Cortex-A9 MPCore #1 (Suspended)
  4 xc7z045

Download the bitstream to the FPGA.

xsdb% source <Vitis Install folder>/scripts/vitis/util/zynqutils.tcl
xsdb% targets -set 1 (APU)
xsdb% rst -system
xsdb% after 3000
xsdb% target -set 4 (xc7z045)
xsdb% fpga -file ./<IP instance name>_ex.runs/impl_1/exdes_wrapper.bit

Set the target processor.

xsdb% targets -set 1 (APU)
xsdb% loadhw ./<vitis_workspace>/<platform_name>/hw/exdes_wrapper.xsa
xsdb% targets -set 1 (APU)
xsdb% ps7_init
xsdb% ps7_post_config
xsdb% targets -set 2 (ARM Cortex-A9 MPCore #0)

Download the software .elf to the FPGA.

xsdb% dow ./<vitis_workspace>/<application_name>_1/Debug/<application_name>_1.elf

Run the software.
```
xsdb% con
```
Exit the XSDB command prompt.
```
xsdb% exit
```
Important: When using the TB-FMCH-HDMI4K example design with the KCU105 board, you must set the FMC VADJ_1V8 Power Rail before programing the FPGA with the bitstream generated in the Example Design flow. The following topic shows how to set the VADJ power rail when using the KCU105 board. For more details about the KCU105 board, see the KCU105 Board User Guide (UG917).