Clocking - 3.2 English

The S_AXI_CPU_IN, VIDEO_IN (AXI4-Stream Video Interface), and AUDIO_IN can be run at their own clock rate. The HDMI link interfaces and native video interface also run at their own clock rate. Therefore, five separate clock interfaces are provided called s_axi_cpu_aclk, s_axis_video_aclk, s_axis_audio_aclk, link_clk, and video_clk respectively.

The audio streaming clock must be greater than or equal to 128 times the audio sample frequency. Because audio clock regeneration is not part of the HDMI 1.4/2.0 TX Subsystem you must provide an audio clock to the application. This can be achieved by using an internal PLL or external clock source.

Important: As stated in HDMI 1.4b Specification section 7.2.4: For any IEC 61937 compressed audio with an IEC 60958 frame rate at or below 192 kHz, the ACR fs value shall be equal to the frame rate. For any such stream with an IEC 60958 frame rate above 192 kHz, the ACR fs value shall be a quarter of the frame rate. Therefore, for HBR audio, while calculating N & CTS, the fs to be used is a quarter of the frame rate. (for example, 768 kHz => 768/4=192 kHz).

The HDMI clock structure is illustrated in the following figure and table.

Figure 1. HDMI Clocking Structure

Table 1. HDMI Clocking
Clock	Function	Freq/Rate	Example¹
TMDS	Source synchronous clock to HDMI interface (This is the actual clock on the HDMI cable).	= 1/10 data rate (for data rates < 3.4 Gbps)	Data rate = 2.97 Gbps TMDS clock = 2.97/10 = 297 MHz
TMDS		= 1/40 data rate (for data rates > 3.4 Gbps)	Data rate = 5.94 Gbps TMDS clock = 5.94/40 = 148.5 MHz
Data	This is the actual data rate clock. This clock is not used in the system. It is only listed to illustrate the clock relations.	= TMDS clock (for data rates < 3.4 Gbps)	Data rate = 2.97 Gbps Data clock = TMDS clock * 1 = 297 MHz
Data		= TMDS clock * 4 (for data rates > 3.4 Gbps)	Data rate = 5.94 Gbps Data clock = TMDS clock * 4 = 594 MHz TMDS clock = 148.5 MHz
Link	Clock used for data interface between the Video PHY layer module and subsystem	For dual pixel video: Clock=data clock/2 For quad pixel video: clock=data clock/4	TMDS clock = 297 MHz Data clock = 297 MHz Link clock = 297 MHz/2=148.5 MHz for dual pixel wide interface Link clock = 297 MHz/4 = 74.25 MHz for quad pixel wide interface Data clock = 594 MHz Link clock = 594 MHz/2=297 MHz for dual pixel wide interface Link clock = 594 MHz/4=148.5 MHz for quad pixel wide interface
Pixel	This is the internal pixel clock. This clock is not used in the system. It is only listed to illustrate the clock relations.	For 8 bpc pixel clock = data clock For 10 bpc pixel clock = data clock/1.25 For 12 bpc pixel clock = data clock/1.5 For 16 bpc pixel clock = data clock/2	Data clock = 297 MHz For 8 bpc pixel clock = 297 MHz For 10 bpc pixel clock = 297/1.25 = 237.6 MHz For 12 bpc pixel clock = 297/1.5 = 198 MHz For 16 bpc pixel clock = 297/1.5 = 148.5 MHz
Video	Clock used for video interface	For dual pixel video clock = pixel clock/2 For quad pixel video clock = pixel clock/4	297 MHz/2 = 148.5 MHz for dual pixel wide interface 297 MHz/4 = 74.25 MHz for quad pixel wide interface For more information on how to choose the correct PLL in the targeted devices, see the Video PHY Controller LogiCORE IP Product Guide (PG230) for non-Versal devices and the HDMI GT Controller LogiCORE IP Product Guide (PG334) for Versal devices.
The examples in the Example column are only for reference and do not cover all the possible resolutions. Each GT has its own hardware requirements and limitations. Therefore, to use the HDMI 1.4/2.0 TX Subsystem with different GT devices, calculate the clock frequencies and make sure the targeted device can support it. When using the HDMI 1.4/2.0 TX Subsystem with the AMD Video PHY Controller IP core, more information can be found in the Video PHY Controller LogiCORE IP Product Guide (PG230). When using the HDMI 1.4/2.0 TX Subsystem with the AMD HDMI GT Subsystem IP core (Versal devices), more information can be found in the HDMI GT Controller LogiCORE IP Product Guide (PG334).

For example, 1080p60, 12 BPC, and 2 PPC are used to show how all the clocks are derived.

Table 2. Example Settings
Video Resolution	Horizontal Total	Horizontal Active	Vertical Total	Vertical Active	Frame Rate (Hz)
1080p60	2200	1920	1125	1080	60

The pixel clock represents the total number of pixels that need to be sent every second.

Therefore,

Pixel clock = Htotal × Vtotal × Frame Rate =2200 x 1125 x 60 =148,500,000 = 148.5 MHz
Video clock = (Pixel clock)/PPC=148.5/2=74.25 MHz
Data clock = Pixel clock × BPC/8=148.5× 12/8=222.75 MHz
Link clock = (Data clock)/PPC=222.75/2=111.375 MHz

Using the associative property in this example,

Data clock = 222.75 MHz < 340 MHz

then

TMDS clock = Data clock = 222.75 MHz

The following figure shows how the clock is distributed in the HDMI 1.4/2.0 TX Subsystem and the relationship to the Video PHY Controller/HDMI GT Subsystem.

Figure 2. HDMI Transmitter Subsystem and Video PHY Controller/HDMI GT Subsystem

The HDMI 1.4/2.0 TX Subsystem can support either AXI4-Stream video or native video.

When AXI4-Stream is selected, the video stream is sent to the HDMI 1.4/2.0 TX Subsystem through the video interface in AXI4-Stream format running at axis_video_aclk. The AXI4-Stream is then processed and converted into native video stream by the AXI4-Stream to Video Out bridge core with the help of the Video Timing Controller module. Because the AXI4-Stream carries only active video data, the AXI4-Stream to Video Out core takes input from an AXI4-Stream slave interface and converts it into a native video stream, which is then fed to the HDMI TX core. The HDMI TX core then packs the native video data with audio data and other auxiliary data into Link Data and sent to the Video PHY Controller /HDMI GT Subsystem at Link Clock.
When the native (or native vectored DE) interface is selected, a video stream is sent to the HDMI 1.4/2.0 TX Subsystem as native video and directly passed to the HDMI TX core. The data is then packed with audio data and other auxiliary data into Link Data and sent to Video PHY Controller/HDMI GT Subsystem at Link Clock.

Based on the system requirement, the Video PHY Controller /HDMI GT Subsystem generates Link Clock and Video Clock for the HDMI 1.4/2.0 TX Subsystem for each targeted video resolution. Meanwhile, the axis_audio_aclk, axis_video_aclk, and AXI4-Lite clocks are free running clocks in the system usually generated by the clock wizard.