Subsystem Facts Table | |
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Subsystem Specifics | |
Supported Device Family 1 |
AMD Versal™ Adaptive SoCs (GTYE5, GTYP) AMD UltraScale+™ Families (GTHE4, GTYE4) AMD UltraScale™ Architecture (GTHE3) AMD Zynq™ 7000 SoC 2 7 series FPGAs (GTXE2) 3 AMD Artix™ 7 FPGAs (GTPE2) 4 |
Supported User Interfaces | AXI4-Lite, AXI4-Stream, Native Video, Native DE Video |
Resources | |
Provided with Subsystem | |
Design Files | RTL |
Example Design | AMD Vivado™ IP integrator and associated software application example |
Test Bench | Not Provided |
Constraints File | XDC |
Simulation Model | Not Provided |
Supported S/W Driver 5 | Standalone, Linux |
Tested Design Flows 6 | |
Design Entry | Vivado Design Suite |
Simulation | Not Provided |
Synthesis | Vivado Synthesis |
Support | |
Release Notes and Known Issues | Master Answer Record: 65911 |
All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
Support web page | |
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