Status and Control Data Channel (SCDC) - 3.2 English

HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235)

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3.2 English
The subsystem supports the following two bits in the SCDC register address offset 0x20 for TMDS configurations (Table 10-19 of the HDMI 2.0 specification).
  • Bit 1: TMDS_Bit_Clock_Ratio
  • Bit 0: Scrambling_Enable

    Automatically handled by the HDMI TX subsystem driver at Stream Start through the API, XV_HdmiTxSs_StreamStart.

Two underlining subcore API drivers are called to set the two SCDC bits, depending on the output video stream.

  • XV_HdmiTx_Scrambler(InstancePtr->HdmiTxPtr);
    • Enables HDMI TX scrambler for HDMI 2.0 video and disable scrambler for HDMI 1.4 video stream
    • Updates the scrambler bit in the sink TMDS Configuration register
  • V_HdmiTx_ClockRatio(InstancePtr->HdmiTxPtr);
    • Sets the TMDS clock ratio bit for HDMI 2.0 video.

An API is also available for the HDMI TX subcore to show the SCDC register values of the sink (for debugging or advanced use cases).

void XV_HdmiTx_ShowSCDC(XV_HdmiTx *InstancePtr);