Product Specification - 1.1 English

AXI Memory Mapped to Stream Mapper LogiCORE IP Product Guide (PG102)

Document ID
PG102
Release Date
2022-08-08
Version
1.1 English

This Figure shows a simplified block diagram of the AXI Memory Mapped to Stream Mapper. The paths designated in blue are related to the AXI4 slave interface (encapsulation), while the paths designated in red are related to the AXI4 master interface (expansion). The data width converters are instantiated optionally when the TDATA width is smaller than the vector of all the signals in the corresponding AXI4-MM channel.

Figure 2-1: Top-Level Block Diagram

X-Ref Target - Figure 2-1

pg102_axi_mm2s_block_diagram_1_x13162.jpg