Feature Summary - 1.1 English

AXI Memory Mapped to Stream Mapper LogiCORE IP Product Guide (PG102)

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1.1 English

The IP module always has two AXI4-Stream interfaces: one master and one slave. The interfaces can be configured to have any TDATA width between 1 and 512 bytes. The interfaces also contain the TKEEP , TLAST , and TID (width of 3 bits) signals.

The IP module can be configured to have either a AXI4-MM master interface, AXI4-MM slave interface or both. The interfaces support variable ADDR, ID and USER signals.

A single clock and active-Low reset is supported.