• Encapsulates AXI4-MM slave interface transactions onto two AXI4-S interfaces.
° Supports AXI4 only.
• Expands AXI4-S transaction into AXI4-MM master interface transactions.
• Supports both encapsulation (S_AXI interface) and expansion (M_AXI interface) in a single module.
° Allows for cross communication with AXI4-MM masters and slaves on both sides of AXI4-S link while only using two AXI4-S interfaces.
• AXI4-S TDATA width can be set independently of the AXI4-MM interface. When necessary, an AXI4-MM transfer can be split into multiple AXI4-S transfers to support desired AXI4-S TDATA width.
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LogiCORE IP Facts Table |
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Core Specifics |
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Supported Device Family (1) |
Versal® ACAP, UltraScale+™ Families, UltraScale Architecture, Virtex®-7, Kintex®-7, Artix®-7 |
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Supported User Interfaces |
AXI4, AXI4-Stream |
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Resources |
See Table: Kintex-7 XC7K325T-FFG900-1 FPGA Resource Estimates . |
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Provided with Core |
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Design Files |
Verilog RTL |
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Example Design |
Verilog |
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Test Bench |
Verilog |
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Constraints File |
Not Provided |
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Simulation Model |
Verilog Behavioral |
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Supported
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N/A |
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Tested Design Flows (2) |
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Design Entry |
Vivado ® Design Suite |
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Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes Guide . |
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Synthesis |
Vivado Synthesis |
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Support |
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Provided by Xilinx at the Xilinx Support web page |
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Notes: 1. For a complete listing of supported devices, see the Vivado IP Catalog. 2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide . |
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