Features - 1.1 English

AXI Memory Mapped to Stream Mapper LogiCORE IP Product Guide (PG102)

Document ID
PG102
Release Date
2022-08-08
Version
1.1 English

Encapsulates AXI4-MM slave interface transactions onto two AXI4-S interfaces.

° Supports AXI4 only.

Expands AXI4-S transaction into AXI4-MM master interface transactions.

Supports both encapsulation (S_AXI interface) and expansion (M_AXI interface) in a single module.

° Allows for cross communication with AXI4-MM masters and slaves on both sides of AXI4-S link while only using two AXI4-S interfaces.

AXI4-S TDATA width can be set independently of the AXI4-MM interface. When necessary, an AXI4-MM transfer can be split into multiple AXI4-S transfers to support desired AXI4-S TDATA width.

LogiCORE IP Facts Table

Core Specifics

Supported Device Family (1)

Versal® ACAP, UltraScale+™ Families, UltraScale Architecture, Virtex®-7, Kintex®-7, Artix®-7

Supported User Interfaces

AXI4, AXI4-Stream

Resources

See Table: Kintex-7 XC7K325T-FFG900-1 FPGA Resource Estimates .

Provided with Core

Design Files

Verilog RTL

Example Design

Verilog

Test Bench

Verilog

Constraints File

Not Provided

Simulation Model

Verilog Behavioral

Supported
S/W Driver

N/A

Tested Design Flows (2)

Design Entry

Vivado ® Design Suite

Simulation

For supported simulators, see the Xilinx Design Tools: Release Notes Guide .

Synthesis

Vivado Synthesis

Support

Provided by Xilinx at the Xilinx Support web page

Notes:

1. For a complete listing of supported devices, see the Vivado IP Catalog.

2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide .