The function of the AXI Memory-Mapped to Stream Mapper IP (axi_mm2s_mapper) is to encapsulate AXI4 Memory-Mapped (AXI4-MM) transactions onto a pair of AXI4-Stream (AXI4-S) interfaces. This allows use of the AXI4-S components which are generally smaller in area, faster in frequency, and allow more flexibility in system designs. The AXI Memory-Mapped to Stream Mapper IP is intended to be used in pairs with one side of the pair converting the AXI4-MM transactions to AXI4-Stream transactions and the other half to perform in the inverse operation to expand the AXI4-S transactions to AXI4-MM transactions.
The AXI4-MM Write Address, Read Address, and Write Data channels are mapped onto one AXI4-S master interface while the Read Data and Write Response channels are mapped onto one AXI4-S slave interface. Together the two AXI4-S interfaces can carry the five AXI4-MM channels by multiplexing them in time. As the burst length of the AXI4-MM transaction is increased, the write data bandwidth lost due to time multiplexing will be minimized. Read data bandwidth can be maximized if the number of write responses sent during read transactions are minimized.
Each IP instance is capable of supporting both AXI4-MM master and AXI4-MM slave interfaces to support master/slave communication on both sides of the axi_mm2s_mapper pairs. The AXI4-S TDATA width can be configured to any arbitrary number of bytes.
IMPORTANT: Each side of the axi_mm2s_mapper pair must be configured identically.
When configuring TDATA widths that are smaller than the encapsulation size of the AXI4-MM transfer, the transfer is broken into multiple AXI4-S transfers and then re-assembled at the endpoint seamlessly.
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X-Ref Target - Figure 1-1 
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