Example Design - 1.1 English

AXI Memory Mapped to Stream Mapper LogiCORE IP Product Guide (PG102)

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1.1 English

The example design output product is available that demonstrates basic core functionality for the customized IP. The example design is an independent Vivado project populated with the customized IP along with additional IPs including another axi_mm2s_mapper instance, example master(s), example slave(s), clocking and reset blocks. A synthesizable top-level HDL file is provided that instantiates and wires together the IPs shown in This Figure . If the parent Vivado project is configured for a Xilinx supported board, then the physical board constraints are also provided. A simulation-only demo test bench for the example design is also provided and discussed in further in the Test Bench .

IMPORTANT: The example design does not exhaustively demonstrate all the features of the IP, and is not a verification test bench.

Figure 8-1: Schematic of the Example Design Top Level

X-Ref Target - Figure 8-1