AXI4-Stream Ports - 1.1 English

AXI Memory Mapped to Stream Mapper LogiCORE IP Product Guide (PG102)

Document ID
PG102
Release Date
2022-08-08
Version
1.1 English
Table 2-4: AXI4-Stream Port Descriptions

Name

Description

S_AXIS_TVALID

M_AXIS_TVALID

TVALID indicates that the master is driving a valid transfer. A transfer takes place when both TVALID and TREADY are asserted.

S_AXIS_TREADY

M_AXIS_TREADY

TREADY indicates that the slave can accept a transfer in the current cycle.

S_AXIS_TDATA [(C_AXIS_TDATA_WIDTH-1):0]
M_AXIS_TDATA [(C_AXIS_TDATA_WIDTH-1):0]

TDATA is the primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes.

S_AXIS_TKEEP [(C_AXIS_TDATA_WIDTH/8-1):0]

M_AXIS_TKEEP [(C_AXIS_TDATA_WIDTH/8-1):0]

TKEEP is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as part of the data stream. Associated bytes that have the TKEEP byte qualifier deasserted are null bytes and can be removed from the stream.

S_AXIS_TLAST

M_AXIS_TLAST

TLAST indicates the boundary of a packet.

S_AXIS_TID [(C_AXIS_TID_WIDTH-1):0]
M_AXIS_TID [(C_AXIS_TID_WIDTH-1):0]

TID provides routing information for the data stream.