Stage 1: Design Optimization - 2022.2 English

The Design Optimization stage is split into sequentially executed steps. These steps are shown in the following diagram.

Figure 1. Design Optimization Steps

Within any given step, multiple implementation commands such as opt_design, place_design, and route_design can be run and QoR suggestions can be generated. For each step, there is a target suggestion list; if any of the generated suggestions appear on the target suggestion list, the design is reset to the required design stage for the suggestion to be successfully applied. If there are no suggestions available on the target suggestion list for a given step, the step is skipped.

The details of the Design Optimization steps are as follows.

Clean Up XDC

The design is checked for any causes that generate an implementation error and timing that is impossible to fix. If an error is picked up, the flow exits. No suggestions are generated or applied at this stage.

Clean Up Utilization

Suggestions that reduce utilization without timing penalty are sought. Other non-utilization-based suggestions might be applied if they can be detected and fixed early in the flow.

Clean Up Clocking

The design is run to place_design to generate accurate clock skew timing numbers. If suggestions exist, the flow is reset.

Note: If there are no suggestions in the Clean Up Utilization and Clean Up Clocking stages, a special stage called First Pass is reported. This is used as a baseline reference to compare with subsequent stages. To reduce compile time, it is not generated if there are suggestions.

Clean Up Congestion

In this step, congestion suggestions are generated after running a limited part of the router to more accurately see the congestion in the design. These suggestions are applied if they exist.

Note: The log file shows that route_design failed when generating this congestion information, but this can be ignored because a full route is not intended at this point.

Clean Up Timing

This phase generates QoR Suggestions based on timing paths that fail timing from the preceding phase's checkpoint and the placer is rerun.

At the end of stage 1 (Design Optimization), it is decided whether to exit or to take the best run to stage 2 (Tool Option Exploration).

To examine the modifications the IDR has made to the design, the QoR suggestion report shows which suggestions are GENERATED and APPLIED at each step. Multiple checkpoints are also generated which can be accessed easily from the design run directory.