Setting Run Report Strategies - 2022.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
Document ID
UG906
Release Date
2022-10-19
Version
2022.2 English

By default, all synthesis and implementation runs will use their corresponding default Reports Strategy. To set a different Report Strategy:

  1. Select a run in the Design Runs window.
  2. Select the Reports tab in the Run Properties window.
  3. Select the strategy from the Report Strategy drop down list.
    Figure 1. Selecting the Report Strategy for an Implementation Run

Two Flow categories are available and each of them provide several pre-defined report strategies as well as any user-defined strategies.

Table 1. Flows and Report Strategies
Flow Report Strategy Note
Synthesis Vivado Synthesis Default Reports Only runs the utilization report at the end of synthesis
No Reports Best strategy to minimize runtime
Implementation Vivado Implementation Default Reports Runs same reports as in Vivado releases prior to 2017.3
UltraFast Design Methodology Reports Runs all reports recommended in the UltraFast Design Methodology Guide for FPGAs and SOCs (UG949)
Performance Explore Reports Same as the default reports, plus additional timing reports after phys_opt_design
Timing Closure Reports Same as UltraFast Design Methodology Reports, plus several report_design_analysis and report_qor_suggestions reports
No Reports Best strategy to minimize runtime

Before launching the run, some reports are greyed out due to one of the following reasons:

  • They are associated with a disabled flow step
  • They are disabled by the user

After the run has completed, all available reports have a green check mark and can be opened by double-clicking on them from the Reports tab. Some reports are not available for one of the following reasons:

  • They are associated with a disabled flow step
  • They are disabled by the user
  • They are enabled in the Incremental Compile runs only
    Figure 2. Viewing Generated Run Reports

    Tip: Several timing summary reports are only generated when setting the legacy project property ENABLE_OPTIONAL_RUNS_STA. Xilinx reserves the right to eliminate this property in a future release. Example: set_property ENABLE_OPTIONAL_RUNS_STA 1 [current_project]