In the Multi-Clock Fanin example shown in the following figure, both clk_a and clk_x are transferring data through combinatorial logic (LUT2) to the synchronizer circuit in the clk_b domain. It is recommended to first synchronize the source data from clk_a and clk_x individually before combining them via some interconnect logic | FPGA logic. This improves the MTBF characteristics of the overall CDC structure, and it prevents glitches to propagate to the destination clock domain.
Figure 1. Multi-Clock Fanin Example
