Design Closure Reports - 2022.2 English

Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

Document ID: UG906
Release Date: 2022-10-19
Version: 2022.2 English

Introduction
Navigating Content by Design Process
Interactive Design Analysis in the IDE
Using the Design Runs Window
Logic Analysis in the IDE
Logic Analysis Features
Using the Netlist Window
Using the Hierarchy Window
Using the Utilization Report
Using the Schematic Window
Searching for Objects Using the Find Dialog Box
Find Criteria
Complex Finds
Find Examples
Tcl Finds
Methodology Analysis
Placement Analysis
Highlighting Placement
Showing Connectivity
Fixed and Unfixed Logic
Cross-Probing to RTL Source
Viewing Metrics
Metrics in a Netlist Design with No Placement
Metrics Requiring a Placed Design
Timing Metrics
Utilization Metrics
Congestion Metrics
Congestion Metrics for 7 Series and UltraScale Device Families
Congestion Metrics for UltraScale+ and Newer Device Families
Routing Analysis
Displaying Routing and Placement
Displaying Routing and Placement when Zoomed Out
Displaying Routing and Placement at Closer Zoom Levels
Viewing Options
Navigating in the Device Window
Viewing Reports and Messages
Viewing and Managing Messages in the IDE
Using the Reports Window
Using the Messages Window
Filtering Messages
Vivado Generated Messages
Synthesis Log
Implementation Log
Using Report DRC
WebTalk Report
Generating and Waiving Design Checks
Creating a Waiver
Creating Waivers from the GUI
Creating Waivers from a Violation Object
Creating Waivers from the Command Line
Creating DRC and Methodology Waivers
Creating CDC Waivers
CDC Rules Precedence
Reporting the Waivers
Exporting the Waivers
Other Waiver Commands
Configurable Report Strategies
Setting Run Report Strategies
Editing Run Report Strategies
Creating New Report Strategies
Timing Analysis
Terminology
Timing Paths
Common Timing Paths
Path from Input Port to Internal Sequential Cell
Internal Path from Sequential Cell to Sequential Cell
Path from Internal Sequential Cell to Output Port
Path from Input Port to Output Port
Timing Paths Example
Timing Path Sections
Source Clock Path
Data Path
Destination Clock Path
Launch and Capture Edges
Timing Analysis Key Concepts
Max and Min Delay Analysis
Max Delay with Setup and Recovery Checks
Min Delay with Hold and Removal Checks
Setup/Recovery (Max Delay Analysis)
Hold/Removal (Min Delay Analysis)
Setup/Recovery Relationship
Hold/Removal Relationship
Path Requirement
Clock Phase Shift
MMCM/PLL Phase Shift Modes
Phase Shift in Timing Reports
Phase Shift in Clock Reports
Clock Skew and Uncertainty
Skew Definition
Clock Pessimism Removal
Optimistic Skew
Clock Uncertainty
Pulse Width Checks
Reading a Timing Path Report
Timing Path Summary Header Examples
Timing Path Summary Header Information
Timing Path Details
Timing Path Details In Text Report
Timing Path Details in Vivado IDE
Verifying Timing Signoff
Reports
General Reports
Report Utilization
Running Report Utilization
Results Name Field
Show Utilization for Specific Cells
Show Utilization for Specific Pblocks
Show SLR Utilization
Show Hierarchical Information with Customized Options
Showing Packthrus
Show Customized Table Report
Showing Prohibit and Fixed Information
Report I/O
Report Clock Utilization
Report Clock Utilization Tables
Clock Primitive Utilization Table
Global Clock Resources Table
Global Clock Source Details Table
Local Clock Details Table
Clock Regions Tables
Key Resource Utilization Table
Global Clocks Tables
Generating the Clock Utilization Report
Results Name Field
Show Clock Roots Only
Write Clock Constraints to File
Export to File
Report DRC
Elaborated Design
Synthesized Design and Implemented Design
Report Route Status
Report Noise
Noise Report Summary Section
Noise Report Messages Section
Noise Report I/O Bank Details Section
Noise Report Links Section
Report Power
Analyzing the Power Report
Reporting Power in a Non-Project Flow
Report RAM Utilization
Running the RAM Utilization Report
Report Control Sets
Report High Fanout Nets
Generating the High Fanout Net Report
Report High Fanout Nets Options
Timing Reports
Report Timing
Running Report Timing
Running Report Timing from the Menu
Running Report Timing from the Clock Interaction Report
Running Report Timing from a Paths List
Report Timing Dialog Box
Targets Tab
Options Tab
Reports
Path Limits
Path Display
Advanced Tab
Timer Settings Tab
Reviewing Timing Path Details
Filtering Paths with Violation
Report Timing Summary
Report Timing Summary Dialog Box
Options Tab
Report Section
Path Limits Section
Path Display Section
Common Section
Advanced Tab
Report Section
File Output Section
Miscellaneous Section
Timer Settings Tab
Interconnect Setting
Multi-Corner Configuration Setting
Disable Flight Delays
Details of the Timing Summary Report
General Information Section
Timer Settings Section
Design Timing Summary Section
Setup Area (Max Delay Analysis)
Hold Area (Min Delay Analysis)
Pulse Width Area (Pin Switching Limits)
Clock Summary Section
Methodology Summary Section
Check Timing Section
Intra-Clock Paths Section
Inter-Clock Paths Section
Other Path Groups Section
User-Ignored Paths Section
Unconstrained Paths Section
Reviewing Timing Path Details
Filtering Paths with Violations
Report Bus Skew
Running Report Bus Skew
Reviewing Bus Skew Path Details
Bus Skew Report Summary Section
Bus Skew Report Per Constraint Section
Report Bus Skew Dialog Box
Report Bus Skew Dialog Box: Options Tab
Report
Path Limits
Path Display
Report Bus Skew Dialog Box: Advanced Tab
File Output
Miscellaneous
Details of the Timing Summary Report
General Information Section
Summary Section
Set Bus Skew Section
Report Clock Networks
Report Clock Interaction
Report Clock Interaction Dialog Box
Results Name Field
Command Field
Open in a New Tab Check Box
Options Tab
Report from Cells Field
Delay Type Field
Significant Digits Field
File Output Section
Timer Settings Tab
Details of the Clock Interaction Report
Matrix Color Coding
Clock Pair Classification
Filtering the Clocks
Clock Pairs Slack Table
Sorting the Data
Selecting Cells and Rows
Table Columns
Exporting the Table
Report Pulse Width
Report Datasheet
Report Datasheet Dialog Box
Report Datasheet Dialog Box: Options Tab
Report Datasheet Dialog Box: Groups Tab
Report Datasheet Dialog Box: Timer Settings Tab
Details of the Datasheet Report
General Information
Input Ports Setup/Hold
Max/Min Delays for Output Ports
Setup Between Clocks
Setup/Hold for Input Buses
Max/Min Delays for Output Buses
Max/Min Delays for Groups
Report Exceptions
Example: Reporting the Timing Exceptions Affecting the Timing Analysis
Reporting Overridden Scoped Timing Exceptions
Reporting the Timing Exceptions Being Ignored
Reporting the Timing Exceptions Coverage
Reporting the Ignored Objects
Exporting the Valid Exceptions
Exporting the Merged Exceptions
Report Exceptions in the Vivado IDE
Report Exceptions Dialog Box
Report Exceptions Dialog Box: Options Tab
Report Section
File Output Section
Miscellaneous Section
Report Exceptions Dialog Box: Targets Tab
Details of the Exceptions Report
General Information Section
Summary Section
Exceptions Section
Ignored Objects Section
Report Clock Domain Crossings
Overview
Terminology
Running Report Clock Domain Crossings
Results Name Field
Clocks Field (From/To)
File Output Field
Options Field
Understanding the Clock Domain Crossings Report Rules
Reviewing the Clock Domain Crossings Report Sections
Summary by Clock Pair
Summary by Type
Detailed Report
Simplified Schematics of the CDC Topologies
Single-Bit Synchronizer
Multi-Bit Synchronizer
Asynchronous Reset Synchronizer
Combinatorial Logic
Fanout
Multi-Clock Fanin
Non-FD Primitive
CE-Controlled CDC
Mux-Controlled CDC
Mux Data Hold CDC
LUTRAM Read/Write Potential Collision
Design Closure Reports
Report QoR Assessment
Overall Assessment Summary
QoR Assessment Details
Methodology Checks
ML Strategy Availability
Challenging Timing Paths
Netlist Objects With DONT_TOUCH Properties
Non-FD High Fanout Nets > 10K
Generating the QoR Assessment Report
Other Command Options
Auto Termination of Runs
Report QoR Suggestions
QoR Suggestion Report
Generating the QoR Suggestion Report
Other Command Options
Writing the Suggestion Object File
Report Design Analysis
Running Report Design Analysis
Results Name Field
Options Tab
Timing Field
Complexity Field
Congestion Field
Advanced Tab
Timer Settings Tab
Interconnect Option
Multi-Corner Configuration Field
Disable Flight Delays Option
Command Line Only Options
Timing Path Characteristics Report
Analyzing Specific Paths
Analyzing the Worst Path along with Preceding and Following Worst Paths
Reading and Interpreting Timing Path Characteristics Reports
Category 1: Timing
Category 2: Logic
Category 3: Physical
Category 4: Property
Category 5: Dynamic Function eXchange Designs
Complexity Report
Analyzing the Design Complexity at the Top Level
Reading and Interpreting a Complexity Report
Congestion Report
Analyzing the Design Congestion
Maximum Congestion Reports
Placer Final Congestion Reporting
Router Initial Congestion Reporting
SLR Net Crossing Reporting
Design QoR Summary
Using Report Design Analysis
Timing Violations
Congestion
Synthesis Analysis and Closure Techniques
Using the Elaborated View to Optimize the RTL
Example
Decomposing Deep Memory Configurations for Balanced Power and Performance
Optimizing RAMB Utilization when Memory Depth is not a Power of 2
Optimizing RAMB Input Logic to Allow Output Register Inference
Improving Critical Logic on RAMB Outputs
Implementation Analysis and Closure Techniques
Intelligent Design Runs
Overview
Stage 1: Design Optimization
Stage 2: Tool Option Exploration
Stage 3: Last Mile Timing Closure
Creating an Intelligent Design Run
Flow Control within Intelligent Design Runs Window
Intelligent Design Run Reports
Intelligent Design Runs Recommendations for Non-Project Users
Supported Families and Design Flows
QoR Suggestions
Executing Suggestions
All Related Commands
Applying the Suggestions
Project Mode
Automatically Generating and Applying Suggestions
Automatic QoR Suggestions and ML Strategies
Automatic QoR Suggestions and the Incremental Flow
Disabling Unwanted Suggestions
Non-Project Mode
RQS in the Incremental Flow
Automatic Removal of Suggestions
Viewing Suggestions in Tcl or Text Format
Supported Families and Flows
Supported Suggestions
Strategy Suggestions
Project Application of Strategy Suggestions
Non-Project Application of Strategy Suggestions
Floorplanning
About Floorplanning
Understanding Floorplanning Basics
Detailed Gate-Level Floorplanning
Advantages of Detailed Gate-Level Floorplanning
Disadvantages of Detailed Gate-Level Floorplanning
Information Reuse
Review I/O and Cell Placement
Adding Placement Constraints
Reusing Placement
Reusing Placement with Incremental Compile
Floorplanning Techniques
Hierarchical Floorplanning
Manual Cell Placement
Using Pblock-Based Floorplanning
Top-Level Floorplan
Analyzing Utilization Statistics
Locking Specific Logic to Device Sites
Fixed and Unfixed Cells
Floorplanning With Stacked Silicon Interconnect (SSI) Devices
Determining if Hold-Fixing is Negatively Impacting the Design
Method 1: Routing without hold fixing
Method 2: Run report_timing -min on Worst Failing Setup Path
Performing NoC Quality of Service Analysis in Versal Devices
Vivado NoC QoS Reporting Examples
Timing Methodology Checks
TIMING-1: Invalid Clock Waveform on Clock Modifying Block
Description
Resolution
Example
TIMING-2: Invalid Primary Clock Source Pin
Description
Resolution
Example
TIMING-3: Invalid Primary Clock on Clock Modifying Block
Description
Resolution
Example
TIMING-4: Invalid Primary Clock Redefinition on a Clock Tree
Description
Resolution
Example
TIMING-5: Invalid Waveform Redefinition on a Clock Tree
Description
Resolution
Example
TIMING-6: No Common Primary Clock Between Related Clocks
Description
Resolution
Example
TIMING-7: No Common Node Between Related Clocks
Description
Resolution
Example
TIMING-8: No Common Period Between Related Clocks
Description
Resolution
TIMING-9: Unknown CDC Logic
Description
Resolution
Example
TIMING-10: Missing Property on Synchronizer
Description
Resolution
Example
TIMING-11: Inappropriate Max Delay with Datapath Only Option
Description
Resolution
TIMING-12: Clock Reconvergence Pessimism Removal Disabled
Description
Resolution
TIMING-13: Timing Paths Ignored Due to Path Segmentation
Description
Resolution
TIMING-14: LUT on the Clock Tree
Description
Resolution
Example
TIMING-15: Large Hold Violation on Inter-Clock Path
Description
Resolution
TIMING-16: Large Setup Violation
Description
Resolution
TIMING-17: Non-Clocked Sequential Cell
Description
Resolution
TIMING-18: Missing Input or Output Delay
Description
Resolution
TIMING-19: Inverted Generated Clock Waveform on ODDR
Description
Resolution
TIMING-20: Non-Clocked Latch
Description
Resolution
TIMING-21: Invalid COMPENSATION Property on MMCM
Description
Resolution
TIMING-22: Missing External Delay on MMCM
Description
Resolution
Example
TIMING-23: Combinational Loop Found
Description
Resolution
TIMING-24: Overridden Max Delay Datapath Only
Description
Resolution
TIMING-25: Invalid Clock Waveform on Gigabit Transceiver (GT)
Description
Resolution
TIMING-26: Missing Clock on Gigabit Transceiver (GT)
Description
Resolution
TIMING-27: Invalid Primary Clock on Hierarchical Pin
Description
Resolution
TIMING-28: Auto-Derived Clock Referenced by a Timing Constraint
Description
Resolution
TIMING-29: Inconsistent Pair of Multicycle Paths
Description
Resolution
TIMING-30: Sub-Optimal Master Source Pin Selection for Generated Clock
Description
Resolution
TIMING-31: Multicycle Path on Phase-Shifted Clock
Description
Resolution
TIMING-32: Bus Skew Constraint Applied on Too Many Signals
Description
Resolution
TIMING-33: Invalid Bus Skew Constraint on Safely Timed Paths
Description
Resolution
TIMING-34: Bus Skew Constraint with Unrealistic Value
Description
Resolution
TIMING-35: No Common Node in Paths with the Same Clock
Description
Resolution
TIMING-36: Invalid Generated Clock due to No Edge Propagation
Description
Resolution
TIMING-37: Bus Skew Constraint Applied on Signals with Fanout
Description
Resolution
TIMING-38: Bus Skew Constraint Applied on Multiple Clocks
Description
Resolution
TIMING-39: Invalid Bus Skew Constraint on Paths that have Too Many Levels of Logic
Description
Resolution
TIMING-40: Max Skew Violation between OSERDESE3 CLK and CLKDIV Pins Crossing SLRs
Description
Resolution
TIMING-41: Invalid Forwarded Clock Defined on an Internal Pin
Description
Resolution
TIMING-42: Path Segmentation Detected in the Clock Tree
Description
Resolution
TIMING-43: Min Period or Min Pulse Width Violation on Gigabit Transceiver (GT)
Description
Resolution
TIMING-44: Unreasonable User Intra-Clock Uncertainty
Description
Resolution
TIMING-45: Unreasonable User Inter-Clock Uncertainty
Description
Resolution
TIMING-46: Multicycle Path with Tied CE Pins
Description
Resolution
Example
TIMING-47: False Path, Asynchronous Clock Group or Max Delay Datapath Only Constraint between Synchronous Clocks
Description
Resolution
Example
TIMING-48: Max Delay Datapath Only Constraint on Latch Input
Description
Resolution
TIMING-49: Unsafe Enable or Reset Topology from Parallel BUFGCE_DIV
Description
Resolution
TIMING-50: Unrealistic Path Requirement between Same-Level Latches
Description
Resolution
TIMING-51: No Common Phase between Related Clocks from Parallel CMBs
Description
Resolution
TIMING-52: No Common Phase between Related Clocks from Spread Spectrum MMCM
Description
Resolution
TIMING-53: No Common Phase between Related Clocks from DPLL
Description
Resolution
TIMING-54: Scoped False Path, Clock Group, or Max Delay Datapath Only Constraint between Clocks
Description
Resolution
TIMING-55: Multiple Clocks Reaching a CMB Deskew Pin
Description
Resolution
TIMING-56: Missing Logically or Physically Excluded Clock Groups Constraint
Description
Resolution
TIMING-57: Unsupported Configuration with PHASESHIFT_MODE and Digital Deskew
Description
Resolution
Report QoR Suggestion RTL Code Change Example
TIMING-201: Add an Output Register to RAM
Verilog Code Example
VHDL Code Example
TIMING-202: Add Extra Pipelining to Wide Multipliers
Verilog Code Example
VHDL Code Example
UTIL-10: Incomplete Case Statement Increasing Control Sets
Verilog Code Example
VHDL Code Example
UTIL-203: Large ROM Inferred using Distributed RAM
Verilog Code Example
VHDL Code Example
Reference Design Files
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
References
Training Resources
Revision History
Please Read: Important Legal Notices

Back to home page