You can place cells on specific locations on the FPGA, such as placing all the I/O ports on a Xilinx 7 series FPGA design. Xilinx recommends that you place the I/Os before attempting to close timing.
The I/O placement can impact the cell placement in the FPGA fabric. Hand placing other cells in the fabric can help provide some consistency to clock logic and macro placement, with the goal of more consistent implementation runs.
| Constraint | Use | Notes |
|---|---|---|
| LOC | Places a gate or macro at a specific site. | SLICE sites have subsites called BEL sites. |
| BEL | Specifies the subsite in the slice to use for a basic element. |