To ensure safe timing on paths with clocks driven by parallel BUFGCE_DIV cells
with a BUFGCE_DIVIDE property set to a value greater than 1 on both, both buffers
<buffer> and <buffer> must use the same enable signal (CE) and the same clear signal (CLR). The
clear signal must not be connected to power or ground. Otherwise, the divided clock
might become phase-shifted to one another in hardware. It is recommended to use the safe
clock startup reset circuitry to reset both BUFGCE_DIV buffers at the same time.