Vivado Simulator Verilog Data Format - 2022.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2022-10-19
Version
2022.2 English

Verilog logic data is encoded in C/C++ using the following struct, defined in xsi.h:

typedef struct t_xsi_vlog_logicval {
    XSI_UINT32 aVal;
    XSI_UINT32 bVal;
} s_xsi_vlog_logicval, *p_xsi_vlog_logicval;

Each four-state bit of Verilog value occupies one bit position in aVal and the corresponding bit position in bVal.

Table 1. Verilog Value Mapping
Verilog Value aVal Bit Value bVal Bit Value
0 0 0
1 1 0
X 1 1
Z 0 1

For two-state SystemVerilog bit values, an aVal bit holds the bit value, and the corresponding bVal bit is unused. Xilinx recommends that you zero out bVal when composing two-state values for xsi_put_value.

Verilog vectors are organized in C/C++ with the right index of the Verilog vector mapped to aVal/bVal bit position 0 and the left index mapped to aVal/bVal bit position <vector size> - 1

Table 2. Verilog Vectors
aVal/bVal Bit Position <vector size> to 31 <vector size> - 1 <vector size> - 2 … ... 1 0

Index of

wire [left:right] vec

(where left > right)

unused left left - 1 … ... right + 1 right

Index of

wire [left:right] vec

(where left < right)

unused left left + 1 … ... right - 1 right

For example, the following table shows the Verilog and C/C++ equivalents of the following Verilog vector.

wire [7:4] w = 4'bXX01;
Table 3. Verilog and C/C++ Equivalents of the Verilog Vector
Verilog Bit Index       7 6 5 4
Verilog Bit Value       X X 0 1
C/C++ Bit Position 31 ... 4 3 2 1 0
aVal Bit Value unused ... unused 1 1 0 1
bVal Bit Value unused ... unused 1 1 0 0

The C/C++ representation of a Verilog vector with more than 32 elements is an array of s_xsi_vlog_logicval, for which the right-most 32 bits of the Verilog vector maps to element 0 of the C/C++ array. The next 32 bits of the Verilog vector maps to element 1 of the C/C++ array, and so forth. For example, the following table shows the mapping of Verilog vector

wire [2:69] vec;

to the C/C++ array

s_xsi_vlog_logicval val[3];
Table 4. Verilog Index Range
Verilog Index Range C/C++ Array Element
vec[38:69] val[0]
vec[6:37] val[1]
vec[2:5] val[3]

Hence, vec[2] maps to val[3] bit position 3, and vec[69] maps to val[0] bit position 0.

A multi-dimensional Verilog array maps to the bits of a s_xsi_vlog_logicval or s_xsi_vlog_logicval array as if the Verilog array were flattened in row-major order before mapping to C/C++.

For example, the two-dimensional array

reg [7:0] mem[0:1];

is treated as if copied to a vector before mapping to C/C++:

reg [15:0] vec;
vec[7:0] = mem[1];
vec[8:15] = mem[0];