Unprotected Models - 2022.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
Release Date
2022.2 English

The unprotected models are released as a source code in the install. You need to compile the model for the target simulator using the compile_simlib utility. For Vivado® simulator, these unprotected models are pre-compiled in the standard <Vivado-install-path>/data/xsim folder where other libraries are compiled. For third party simulators, these models must be compiled using compile_simlib. The following un-protected models are delivered as part of Vivado installation:

  • aie_xtlm
  • axi_tg_sc
  • axis_dwidth_converter_sc
  • axis_switch_sc
  • common_cpp
  • common_rpc
  • debug_tcp_server
  • emu_perf_common
  • noc_sc
  • pl_fileio
  • remote_port_c
  • remote_port_sc
  • rwd_tlmmodel
  • sim_ddr
  • sim_qdma_cpp
  • sim_qdma_sc
  • sim_xdma_cpp
  • sim_xdma_sc
  • tlm_ext
  • xtlm
  • xtlm_ap_ctrl
  • xtlm_ipc
  • xtlm_simple_interconnect
  • xtlm_trace_model
These simulation model sources are present in the following installation path:

The following IP support SystemC simulation:

  • processing_system7_v5_5_6
  • versal_cips_v3_2_0
  • zynq_ultra_ps_e_v3_2_6
  • zynq_ultra_ps_e_v3_3_8
Note: GCC version to compile these models should be supported version as mentioned in this user guide.