Packed Struct/Union - 2022.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2022-10-19
Version
2022.2 English

When using a packed struct or union type, an equivalent SystemVerilog type, svLogicVecVal or svBitVecVal, is created on the DPI C side.

Examples

SystemVerilog type
typedef struct packed {
        int i;
        bit b;
        reg [3:0]r;
        logic [2:0] [4:8][9:1] l;
    } sType;
    sType c_obj;
   sType [3:2] c_obj1[5];
C type
svLogicVecVal c_obj[SV_PACKED_DATA_NELEMS(172)];
svLogicVecVal c_obj1[5][SV_PACKED_DATA_NELEMS(344)];

Arrays, both packed and unpacked, are represented as arrays of svLogicVecVal or svBitVecVal.