Fixed and Floating Point Packages - 2022.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2022.2 English

Fixed and floating point packages used by the Vivado simulator are the new enhanced IEEE standard packages introduced in VHDL-2008. If you are using the VHDL-93 standard fixed or floating package, that may work in Vivado synthesis, however you must edit your VHDL source file for simulation.

For example, if you are using the following syntax for the fixed package in Vivado synthesis:

library ieee;
use ieee.fixed_pkg.all;

Change this to the following syntax in VHDL-2008 for use in the Vivado simulator:

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

See this link in the Vivado Design Suite User Guide: Synthesis (UG901) for more information about fixed and floating packages in Vivado Synthesis.

Similar changes will apply for floating package too.