Using Automated Testbench Generation on Example Design - 2022.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2022.2 English
For demo purpose, let us use the BFT example design shipped with Vivado IDE.
  1. Open the BFT example design in Vivado IDE.
  2. Call launch_simulation with Vivado as the selected simulator. You should see the ports shown in the following waveform.

  3. Select the desired scope for which you want to generate testbench as shown in the following figure:

  4. Right-click the selected scope and select Generate VCD Port.

  5. Delete all existing signals on the waveform and select Add to Wave Window for the selected scope.
    Note: Step 5 will be used to demonstrate that the generated testbench is driving the design unit correctly.
  6. Use restart, run 2000 ns and close_vcd -ports commands on Tcl console to dump the signal activity. This logs the signal from time 0 to 2000 ns on the waveform as shown in the following figure:

  7. Use create_testbench -name demo_tb -add_to_simset demo_simset -set_as_top command on Tcl console to generate testbench. This creates your testbench with the module name demo_tb and creates a demo_simset with this testbench as top module.

  8. Use launch_simulation command to run simulation with the newly generated testbench.
  9. Compare the input/output of the waveform with waveform of your original design, notice that the input/output are same.

This is how you can create testbench for your sub-design and use the generated testbench independently with any standard simulator.