VHDL integer Type - 2022.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2022-10-19
Version
2022.2 English

A single VHDL integer value is represented in C/C++ as an int.

Example code:

// Put 1234 (decimal) on signal "myInt," where "myInt" is defined as
// signal myInt : integer;
const int intVal = 1234;
int myInt = loader.get_port_number("myInt");
loader.put_value(myInt, &intVal);