Important: Confirm the compiled library location (the path at which
compile_simlib was invoked or the one you specified with the -directory option) before running a third-party simulation.From the Vivado IDE, you can compile, elaborate, and simulate the design based on the simulation settings and launch the simulator in a separate window.
When you run simulation prior to synthesizing the design, the simulator runs a behavioral simulation. Following each successful design step (synthesis and implementation), the option to run a functional or timing simulation becomes available. You can initiate a simulation run from the Flow Navigator or by typing in a Tcl command.
From the Flow Navigator, click Run Simulation, and select the type of simulation you want to run, as shown in the following figure:
Figure 1. Types of Simulation
To use the corresponding Tcl command, type: launch_simulation
Tip: This command provides a
-scripts_only option that can be used to write a DO or SH file, depending on the target simulator. Use the DO or SH file to run simulations outside the IDE.
Note: If you are running VCS simulator outside of Vivado, make sure to use
-full64 switch. Otherwise, the simulator will not run if the design
contains Xilinx IP.Important: Use the following command to run the 32-bit Simulator:
set_property 32bit 1 [current_fileset -simset]
Note:
Xilinx Verification IP (VIP) uses SystemVerilog construct. If you are
using any IP which instantiates VIP, make sure that your simulator supports
SystemVerilog.