The code examples below show how to force a signal to a specified value using the
add_force
command. A simple verilog circuit is provided. The
first example shows the interactive use of the add_force
command
and the second example shows the scripted use.
Example 1: Adding Force
The following code snippet is a Verilog circuit:
module bot(input in1, in2,output out1);
reg sel;
assign out1 = sel? in1: in2;
endmodule
module top;
reg in1, in2;
wire out1;
bot I1(in1, in2, out1);
initial
begin
#10 in1 = 1'b1; in2 = 1'b0;
#10 in1 = 1'b0; in2 = 1'b1;
end
initial
$monitor("out1 = %b\n", out1);
endmodule
You can invoke the following commands to observe the effect of
add_force
:
xelab -vlog tmp.v -debug all
xsim work.top
At the command prompt, type:
add_force /top/I1/sel 1
run 10
add_force /top/I1/sel 0
run all
You can use the add_force
Tcl
command to force a signal, wire, or register to a specified value:
add_force [-radix <arg>] [-repeat_every <arg>] [-cancel_after <arg>] [-quiet]
[-verbose] <hdl_object> <values>...
For more info on this and other Tcl commands, see the Vivado Design Suite Tcl Command Reference Guide (UG835).
Example 2: Scripted Use of add_force with remove_forces
The following is an example Verilog file, top.v, which instantiates a counter. You can use this file in the following command example.
module counter(input clk,reset,updown,output [4:0] out1);
reg [4:0] r1;
always@(posedge clk)
begin
if(reset)
r1 <= 0;
else
if(updown)
r1 <= r1 + 1;
else
r1 <= r1 - 1;
end
assign out1 = r1;
endmodule
module top;
reg clk;
reg reset;
reg updown;
wire [4:0] out1;
counter I1(clk, reset, updown, out1);
initial
begin
reset = 1;
#20 reset = 0;
end
initial
begin
updown = 1; clk = 0;
end
initial
#500 $finish;
initial
$monitor("out1 = %b\n", out1);
endmodule
Command Example
- Create a file called add_force.tcl with following command:
create_project add_force -force add_files top.v set_property top top [get_filesets sim_1] set_property -name xelab.more_options -value {-debug all} -objects [get_filesets sim_1] set_property runtime {0} [get_filesets sim_1] launch_simulation -simset sim_1 -mode behavioral add_wave /top/*
- Invoke the Vivado Design Suite in Tcl mode, and source the add_force.tcl file.
- In the Tcl Console, type:
set force1 [add_force clk {0 1} {1 2} -repeat_every 3 -cancel_after 500] set force2 [add_force updown {0 10} {1 20} -repeat_every 30] run 100
Observe that the value of
out1
increments as well as decrements in the Wave window. You can observe the waveforms in the Vivado IDE using thestart_gui
command.Observe the value of
updown
signal in the Wave window. - In the Tcl Console, type:
remove_forces $force2 run 100
Observe that only the value of
out1
increments. - In the Tcl Console, type:
remove_forces $force1 run 100
Observe that the value of
out1
is not changing because theclk
signal is not toggling.