Simulating in Batch or Scripted Mode in Vivado Simulator - 2022.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2022.2 English

This chapter describes the command line compilation and simulation process.

Vivado supports an integrated simulation flow where the tool can launch Vivado simulator, or a third party simulator from the IDE. However, many users also want to run simulation in batch or scripted mode in their verification environment, which may include system-level simulation, or advanced verification such as UVM. The Vivado Design Suite supports batch or scripted simulation in the Vivado simulator.

This chapter describes a process to gather the needed design files, to generate simulation scripts for your target simulator, and to run simulation in batch mode. The simulation scripts can be generated for a top-level HDL design, or for hierarchical modules, managed IP projects, or block designs from Vivado IP integrator. Batch simulation is supported in both project and non-project script-based flow.