This tutorial contains several labs as described in the following:
- Lab 1
- Open a modified version of the Xilinx wave_gen example design that is missing a FIFO; locate and customize the IP in the catalog; and instantiate the IP into the design.
- Lab 2
- Create and customize IP using the Manage IP flow. Create a project, include an IP from the IP catalog as the top-level source; customize and verify the IP. Optionally, use the customized IP as a black box in a third-party synthesis flow.
- Lab 3
- Write and run a Tcl script using the Vivado® Design Suite to create a project, add IP, upgrade IP, disable IP sources, and generate output products including synthesized design checkpoints (DCP).
- Lab 4
- Write and run a Non-Project Tcl script using the Vivado Design Suite to read in IP sources, upgrade IP, disable IP sources, and generate output products including a design checkpoint (DCP) file.