Step 1: Read the Design Source Files - 2022.1 English

Vivado Design Suite Tutorial: Designing with IP (UG939)
Document ID
UG939
Release Date
2022-06-10
Version
2022.1 English
  1. Invoke a text editor of your choice, such as Emacs, VI, or Notepad; or launch the Text Editor from within the Vivado® IDE.
  2. Save a new file called non_project_run.tcl in <Extract_Dir>/lab_4.

    In Lab 4, you started your project by creating a project; here you will begin by creating an in- memory design, and reading source files. However, you want to first make sure that the Tcl script is in the right location to find source files referenced by the script.

  3. Add the following line to your Tcl script to change to the appropriate directory for this lab:
    cd <extract_dir>4/lab_4
  4. You can replace the <extract_dir> variable with the actual path to your tutorial data. For example: C:/ug939-design-files/lab_4.

    A default target part is used unless you specify another. This target part is used for all IP that are added to the design, otherwise the default part for the Vivado® Design Suite is used. Additionally, setting the target part removes the need to specify a part when synthesizing the top-level design, or any IP for out-of-context synthesis.

  5. Add the following to your script to set the part to be used:
    set_part xc7k70tfbg484-3
    Recommended: In Non-Project Mode, there is no project part unless you create an in-memory project. If you do not create an in-memory project, the IP output products are generated using the default part of the Vivado Design Suite release. This default part might not be the intended target part specified by the synth_design command, and can result in mismatched synthesis results between the IP and the top-level design in Non-Project Mode designs. To to see how a target part is specified for a customized IP see Lab 2: Creating and Managing Reusable IP for more information on managing IP customizations.

    Now you are ready to read the source files for the design. In Project Mode, you use commands such as add_files and import_files to add source files to the project.

    In Non-Project Mode, you can use add_files, which calls the appropriate lower-level command, but it is more typical to directly read the file type. This is similar to an ASIC tool flow. For this lab, you are working with Verilog source files and will use read_verilog to read them.

  6. Add the following line to your script to read all the Verilog source for this project:
    read_verilog [glob ../Lab_3_4_sources/HDL/*.v]
    Tip: The glob command is a built-in Tcl command that creates a list out of the specified objects. Alternatively, you can make a Tcl list to pass to read_verilog, or use a separate read_verilog command for each file.