Customizing the FIFO Generator - 2022.1 English

Vivado Design Suite Tutorial: Designing with IP (UG939)

Document ID: UG939
Release Date: 2022-06-10
Version: 2022.1 English

Designing with IP Overview
Navigating Content by Design Process
Hardware, IP, and Platform Development
System Integration and Validation
Introduction
Tutorial Description
Hardware and Software Requirements
Locating and Preparing the Tutorial Design Files
Customizing the FIFO Generator
Introduction
Step 1: Open the Project
Step 2: Customize the FIFO Generator
Step 3: Instantiate IP into the Design
Step 4: Synthesize the Design
Conclusion
Creating and Managing Reusable IP
Introduction
Step 1: Start a Manage IP session
Step 2: Customize the FIFO Generator
Step 3: Customize the Clocking Wizard
Step 4: Use Third-Party Simulators
Get the Required Simulation Files
Structural Netlists for Simulation
Step 5: Add Additional IP
Step 6: Use Third-Party Synthesis Tools
Step 7: Create a Netlist Project
Create a Non-Project Third-Party Script
Conclusion
Scripting the Project Mode
Introduction
Step 1: Create a Project
Step 2: Add RTL Source Files
Step 3: Add XDC Constraints
Step 4: Add Existing IP
Step 5: Disable the IP XDC Files
Step 6: Upgrade an IP
Step 7: Setup Design Runs for IP
Create and Launch a Design Run for the Block Memory Generator IP
Step 8: Launch Synthesis and Implementation
Step 9: Run the Script
Source the Tcl Script
Conclusion
Scripting the Non-Project Mode
Introduction
Step 1: Read the Design Source Files
Step 2: Add Existing IP
Step 3: Disable XDC Files
Step 4: Upgrade IP
Step 5: Create DCP for IP
Step 6: Run Synthesis
Step 7: Run Implementation
Step 8: Run the Script
Source the Tcl Script
Conclusion
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

Back to home page