NGC2EDIF
command to migrate the NGC file to EDIF format for importing. However,
Xilinx®
recommends using native
Vivado®
IP rather than XST-generated NGC format files going
forward.You will also import IP cores into the project. There are four IP cores used in this design:
- Accumulator
- Vivado 2022.1 version with all output products.
- Block Memory Generator
- An outdated version of native Vivado Design Suite IP with no output products generated.
- FIFO Generator
- Vivado 2022.1 version with all output products, including DCP.
- Clock Wizard
- Vivado 2022.1 version with no output products.
All of these IP, are native Vivado cores. They have already been customized, and have a Xilinx Core Instance (XCI) file.
import_ip -files { \
../Lab_3_4_sources/IP/Accumulator/c_accum_0.xci \
../Lab_3_4_sources/IP/blk_mem/blk_mem_gen_v7_3_0.xci \
../Lab_3_4_sources/IP/clk_wiz/clk_wiz_0.xci \
../Lab_3_4_sources/IP/char_fifo/char_fifo.xci}
WARNING: [IP_Flow 19-2162] IP 'blk_mem_gen_v7_3_0' is locked:
* IP definition 'Block Memory Generator (7.3)' for IP 'blk_mem_gen_v7_3_0' has a newer major version in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
The c_accum_0 is current and all output products are present so no warning messages display when importing.
The blk_mem_gen_v7_3_0 core is not the latest version in the IP catalog. There are no output products to drive synthesis or simulation, so it will have to be upgraded to the latest version. You will upgrade this IP in a subsequent step. If no upgrade path is available, you must recreate the IP.
For the clk_wiz_0, no output products were found with the XCI customization (.xci) file, but the IP is the current version in the IP catalog. You will manually generate the output products for this IP in the next step.