Step 8: Run the Script - 2022.1 English

Vivado Design Suite Tutorial: Designing with IP (UG939)

Document ID
Release Date
2022.1 English

You are now ready to run the Tcl script. Your script should be similar to the following:

#Step 1: Reading RTL
cd C:/ug939-design-files/lab_4
set_part xc7k70t-fbg484-3
read_verilog [glob ../Lab_3_4_sources/HDL/*.v]
#Step 2: Adding Existing IP
read_ip ../Lab_3_4_sources/IP/char_fifo/char_fifo.xci
read_ip ../Lab_3_4_sources/IP/Accumulator/c_accum_0.xci
file mkdir IP/blk_mem
file mkdir IP/clk_wiz
file copy -force ../Lab_3_4_sources/IP/blk_mem/blk_mem_gen_v7_3_0.xci ./IP/blk_mem
file copy -force ../Lab_3_4_sources/IP/clk_wiz/clk_wiz_0.xci ./IP/clk_wiz
read_ip ./IP/blk_mem/blk_mem_gen_v7_3_0.xci
read_ip ./IP/clk_wiz/clk_wiz_0.xci
#Step 3: Disable DCP and XDC
set_property generate_synth_checkpoint false [get_files clk_wiz_0.xci]
generate_target all [get_ips clk_wiz_0]
set clk_wiz_xdc [get_files -of_objects [get_files \
clk_wiz_0.xci] -filter {FILE_TYPE == XDC}]
set_property is_enabled false [get_files $clk_wiz_xdc]
#Step 4: Upgrade IP
set locked [get_property IS_LOCKED [get_ips blk_mem_gen_v7_3_0]]
set upgrade [get_property UPGRADE_VERSIONS [get_ips blk_mem_gen_v7_3_0]]
if {$upgrade != "" && $locked} {
upgrade_ip [get_ips blk_mem_gen_v7_3_0]}
generate_target all [get_ips blk_mem_gen_v7_3_0]
generate_target all [get_ips c_accum_0]
generate_target all [get_ips char_fifo]
#Step 5: Creating DCP for IP
synth_ip [get_ips blk_mem_gen_v7_3_0]
synth_ip [get_ips c_accum_0]
synth_ip [get_ips char_fifo]
#Step 6: Running Synthesis
read_xdc ../Lab_3_4_sources/Constraints/top_timing.xdc
synth_design -top sys_integration_top
write_checkpoint -force post_synth.dcp
report_timing_summary -file timing_syn.rpt
#Step 7: Running Implementation
read_xdc ../Lab_3_4_sources/Constraints/top_physical.xdc
write_checkpoint -force post_place.dcp
report_timing -file timing_place.rpt
write_checkpoint -force post_route.dcp
report_timing_summary -file timing_summary
write_bitstream -force sys_integration_top.bit