Step 2: Add RTL Source Files - 2022.1 English

For this script, you will be copying all the RTL source files into the local project directory.

Because all the HDL files that you need are located in <extract_dir>/lab_3/sources, you can add the entire directory directly.

add_files -scan_for_includes ../Lab_3_4_sources/HDL
import_files

The -scan_for_includes option scans the Verilog source files for any `include statements, and also adds these referenced files as source files to the project. By default, `include files are not added to the fileset.

The use of ../Lab_3_4_sources provides a relative path for locating the source files from where the Tcl script is being run. Recall that the project_run.tcl script is being created in the <extract_dir>/lab_3 directory, so the ../Lab_3_4_sources folder is found in the directory above that.