Step 6: Use Third-Party Synthesis Tools - 2022.1 English

Vivado Design Suite Tutorial: Designing with IP (UG939)

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2022.1 English

Xilinx® IP delivered with the Vivado® Design Suite supports synthesis using the Vivado synthesis tool only. The user logic can be synthesized using a supported third-party synthesis tools, such as Synopsys® Synplify Pro or Mentor Graphics® Precision.

The Vivado Design Suite generates a Verilog/VHDL stub file for each IP customization that can be used by third-party synthesis tools to infer a black box for the Vivado IP.

Vivado automatically creates the stub file if a synthesized DCP is generated for the IP, which is the default behavior of the tool. Because it is important that the third-party synthesis tool does not insert I/O buffers for ports that are connected to the Vivado IP, the <ip_name>_stub.v contains synthesis directives to prevent I/O buffer insertion.

This lab has you use a Manage IP project to create and customize two IP used in the sample design.

  • To avoid requiring access to a third-party synthesis tool you are provided an EDIF produced using Synplify Pro.
  • You are also provided two Xilinx Design Constraints (XDC) files for constraining the design during implementation.
  • An optional stage is provided on how to perform simulations with the IP.
  • You create a netlist project and combine the IP with the netlist produced by the third-party synthesis tool.
  • A script is provided to demonstrate how you would use a non-project flow to bring the sources together for implementation.