Structural Netlists for Simulation - 2022.1 English

Vivado Design Suite Tutorial: Designing with IP (UG939)
Document ID
UG939
Release Date
2022-06-10
Version
2022.1 English

Depending on which Simulator Language you select during the Manage IP project creation (see the following figure) the results of the get_files commands above differs.

With some IP, you might not be able to do behavioral simulation if you did not specify support for a Mixed simulator, and instead selected Verilog or VHDL.

You would need to run simulations using a structural netlist, which the Vivado Design Suite produces automatically when a synthesized design checkpoint is available.

If the IP can deliver behavioral simulation files based upon your selected simulator language, when generating the output products you see Behavioral Simulation listed as an output product.

However, if the IP does not deliver simulation files for the selected simulator language you see Structural Simulation as shown in the following figure.

Tip: Structural simulation output products, for both Verilog and VHDL, are always created when a synthesized design checkpoint is produced. Querying the simulation files with get_files will vary depending on whether behavioral simulation was possible with the selected simulator language setting.