Step 3: Instantiate IP into the Design - 2022.1 English

Vivado Design Suite Tutorial: Designing with IP (UG939)

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2022.1 English
You will now instantiate the IP customization into the design by copying and pasting the Verilog Instantiation Template into the appropriate Verilog source file in your project and modifying the signals.
  1. In the IP Sources tab of the Sources window, click the Instantiation Template to expand it and then double-click the char_fifo.veo file to open the template in the Vivado® Text Editor.
  2. Scroll down to line 57 of the template file, and select and copy the module instantiation text, as shown in the following figure.

    Next, you paste the instantiation template into the appropriate RTL source file. In this case, you paste the module into the top-level of the design, in the wave_gen.v source file.

  3. Open this file for editing from the Hierarchy tab of the Sources view, by double-clicking wave_gen.v. The following figure shows the file.

  4. Go to line 337, which contains a comment stating the Character FIFO should be instanced at this point.
  5. Paste the template code into the file as shown in the following figure.

    Because it is only a template for the module, you need to do some local editing to make the module work in your design.

    1. In line 338 (approximately) above where you pasted the instantiation, change the module name from your_instance_name to char_fifo_i0.
    2. Change the wire names as follows, to connect the ports of the module into the design:
      char_fifo char_fifo_i0 (
      .rst(rst_i), // input wire rst
      .wr_clk(clk_rx), // input wire wr_clk
      .rd_clk(clk_tx), // input wire rd_clk
      .din(char_fifo_din), // input wire [7 : 0] din
      .wr_en(char_fifo_wr_en), // input wire wr_en
      .rd_en(char_fifo_rd_en), // input wire rd_en
      .dout(char_fifo_dout), // output wire [7 : 0] dout
      .full(char_fifo_full), // output wire full
      .empty(char_fifo_empty), // output wire empty
      .wr_rst_busy(wr_rst_busy),  // output wire wr_rst_busy 
      .rd_rst_busy(rd_rst_busy)  // output wire rd_rst_busy 
  6. In the Text Editor menu, click the Save File button () to save the changes to the wave_gen.v file.

    Notice that the Hierarchy, Libraries, and Compile Order tabs update to indicate that the IP is instanced into the design, as seen in the following figure.