Step 2: Customize the FIFO Generator - 2022.1 English

Vivado Design Suite Tutorial: Designing with IP (UG939)
Document ID
UG939
Release Date
2022-06-10
Version
2022.1 English
You can work with the IP catalog by searching with a keyword or browsing through the categories.
Tip: For a complete description of the Customize IP dialog box, and its use, see Customizing the FIFO Generator. This Lab assumes that you have previously completed Lab 1, and are familiar with the concepts covered in that lab.
  1. In the IP catalog search bar, type: fifo.
  2. Double-click the FIFO Generator from the Memories & Storage Elements group.

    The Customize IP dialog box opens, as shown in the following figure (this is not the original setting; it shows the change that you make to the customization).



  3. At the top of the Customize IP dialog box, change the Component Name to char_fifo.
  4. In the Basic tab:
    • Select the default Interface Type of Native.
    • From the Fifo Implementation menu, set Independent Clocks Block RAM.
  5. In the Native Ports tab:
    • Set the Read Mode to First Word Fall Through.
    • Set the Write Width to be 8 bits.
    • Click the Read Width field to adjust it automatically to 8 bits as well.
  6. Select the Summary tab.

    The Summary page displays a summary of all the options selected as well as listing resources used for this configuration. The summary for the FIFO Generator core should look like the following figure. For this configuration you will see you are using one 18K BRAM.



  7. Verify that the information is correct as shown, and click OK to generate the customized IP core for use in your design.

    The Generate Output Products popup appears, as seen in the following figure. When creating a repository of customized IP using the Managed IP flow, generate all output products, including the design checkpoint (DCP), for each IP. A specific release of the Vivado tools only supports a single version of an IP core. You cannot re-customize or generate outputs for a prior version of IP in the Vivado Design Suite. Instead, you would need to update the IP to the latest version if you have not preserved the needed output products.

    Important: Only one version of an IP is supported in a given release of the Vivado tool. To use older versions of an IP, ALL output products must be available in your custom IP repository.
  8. Click the Generate button to create the output products, as shown in the following figure.

  9. When prompted, click OK.

    To reduce synthesis runtime for a design using one or more customized IP cores, the IP are pre-synthesized as a standalone module by default, with the netlist saved in a synthesized checkpoint file (DCP).

    During synthesis of the overall design, the Vivado synthesis infers a black box for the IP.

    During implementation, the netlists from the DCP files are linked into the design. This flow is scriptable in Tcl for both Project and Non-Project Mode.

    To create the synthesized checkpoint file, the Vivado IDE creates and launches a corresponding out-of-context module run.

    This run automatically launches, and when synthesis completes, the char_fifo directory contains the following additional files:
    char_fifo.dcp
    The synthesis design checkpoint, which contains a netlist for the IP.
    char_fifo_stub.v
    A Verilog port module for use with third-party synthesis tools to infer a black box for the IP. The stub contains directives for Synplify Pro to not insert IO buffers, this may require editing for other third-party synthesis tools.
    char_fifo netlist files, sim_netlist.v, and sim_netlist.vhd
    A Verilog and VHDL netlist for functional simulation of the IP core.

    If you are using a third-party synthesis tool for the design, a Verilog stub file with the port declarations, or a VHDL component declaration, is required to infer the black box.

    The Vivado Design Suite automatically creates this file along with the synthesis design checkpoint (DCP) when generating the output products.

    Customized IPs can be referenced using the XCI file from both Project and Non-Project Mode.

    In a project-based design, Xilinx recommends that you do not copy sources into the local project structure, but rather reference them from your custom IP repository. For more information on Project Mode and Non-Project Mode, see the Vivado Design Suite User Guide: Design Flows Overview (UG892).

  10. Examine the <extract_dir>/lab_2/my_ip location.

    Notice that three directories are created, as shown in the following figure:

    • The IP customization (char_fifo) containing the XCI file, which has all the customization information for the IP, and all the output products generated.
    • The IP Project (managed_ip_project) which you created in this lab to customize the char_fifo IP and manage the output products, including the post synthesis DCP.
    • The support files for IP (ip_user_files) which contains simulation scripts for all supported simulators, copies of the instantiation templates, stub files for use with third party synthesis tools, and static RTL files used for simulation. All these files with the exception of the simulation scripts are copied from the IP customization directory (in this case char_fifo). See the Vivado Design Suite User Guide: Designing with IP (UG896) for more details on the ip_user_files directory.

  11. Examine the Sources window as shown in the following figure, to see the generated output products in the Manage IP project.

    The generated output products for the char_fifo core include the instantiation template, synthesis files, simulation files, synthesized design checkpoint, functional simulation netlists as well as stub files for use with third-party synthesis tools.

    Note: The FIFO customization created in this lab is the same as the one from Lab 1: Customizing the FIFO Generator. If you want to add existing IP into a Managed IP project, select File > Add Existing IP.
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