Accessing Hardware Design Data - 2022.1 English

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)
Document ID
UG1400
Release Date
2022-04-26
Version
2022.1 English

# Opening the hardware design

hsi::open_hw_design base_zynq_design_wrapper.xsa
base_zynq_design_imp

# List loaded hardware designs

hsi::get_hw_designs
base_zynq_design_imp

# Switch to current hardware design

hsi::current_hw_design
base_zynq_design_imp

# Report properties of the current hardware design

common::report_property [hsi::current_hw_design]
Table 1. Example Table
Property Type Read Only Visible Value
ADDRESS_TAG string* true true
  • base_zynq_design_i/
  • ps7_cortexa9_0:base_zynq_design_ibase_zynq_design_i/
  • ps7_cortexa9_1:base_zynq_design_i
BOARD string true true xilinx.com:zc702:part0:1.1
CLASS string true true hw_design
DEVICE string true true 7x020
FAMILY string true true zynq
NAME string true true base_zynq_design_imp
PACKAGE string true true clg484
PATH string true true /scratch/demo//base_zynq_design.hwh
SPEEDGRADE string true true 1
SW_REPOSITORIES string* true true  
TIMESTAMP string true true <current date and time>
VIVADO_VERSION string true true 2014.3

# List the .xsa files in the container

hsi::get_hw_files
base_zynq_design.hwh ps7_init.c ps7_init.h ps7_init_gpl.c
ps7_init_gpl.h ps7_init.tcl ps7_init.html
base_zynq_design_wrapper.mmi base_zynq_design_bd.tcl

# Filter the .bit files

hsi::get_hw_files -filter {TYPE==bit}
base_zynq_design_wrapper.bit

# List of external ports in the design

hsi::get_ports
DDR_cas_n DDR_cke DDR_ck_n DDR_ck_p DDR_cs_n DDR_reset_n
DDR_odt DDR_ras_n
DDR_we_n DDR_ba DDR_addr DDR_dm DDR_dq DDR_dqs_n DDR_dqs_p
FIXED_IO_mio
FIXED_IO_ddr_vrn FIXED_IO_ddr_vrp FIXED_IO_ps_srstb
FIXED_IO_ps_clk
FIXED_IO_ps_porb leds_4bits_tri_o

# Reports properties of an external port

common::report_property [hsi::get_ports leds_4bits_tri_o]
Table 2. Example Table
Property Type Readonly Visible Value
CLASS string true true port
CLK_FREQ string true true  
DIRECTION string true true 0
INTERFACE bool true true 0
IS_CONNECTED bool true true 0
LEFT string true true 3
NAME string true true leds_4bits_tri_o
RIGHT string true true 0
SENSITIVITY enum true true  
TYPE enum true true undef
# List of IP instances in the design
hsi::get_cells
axi_bram_ctrl_0 axi_gpio_0 blk_mem_gen_0
processing_system7_0_axi_periph_m00_couplers_auto_pc
processing_system7_0_axi_periph_s00_couplers_auto_pc
processing_system7_0_axi_periph_xbar
rst_processing_system7_0_50M ps7_clockc_0 ps7_uart_1
ps7_pl310_0 ps7_pmu_0 ps7_qspi_0
ps7_qspi_linear_0 ps7_axi_interconnect_0 ps7_cortexa9_0
ps7_cortexa9_1 ps7_ddr_0
ps7_ethernet_0 ps7_usb_0 ps7_sd_0 ps7_i2c_0 ps7_can_0
ps7_ttc_0 ps7_gpio_0
ps7_ddrc_0 ps7_dev_cfg_0 ps7_xadc_0 ps7_ocmc_0
ps7_coresight_comp_0 ps7_gpv_0 ps7_scuc_0
ps7_globaltimer_0 ps7_intc_dist_0 ps7_l2cachec_0 ps7_dma_s
ps7_iop_bus_config_0 ps7_ram_0
ps7_ram_1 ps7_scugic_0 ps7_scutimer_0 ps7_scuwdt_0
ps7_slcr_0 ps7_dma_ns ps7_afi_0 ps7_afi_1
ps7_afi_2 ps7_afi_3 ps7_m_axi_gp0
#List of processors in the design
hsi::get_cells -filter {IP_TYPE==PROCESSOR}
ps7_cortexa9_0 ps7_cortexa9_1
# Properties of IP instance
common::report_property [hsi::get_cells axi_gpio_0]
Table 3. Example Table
Property Type Readonly Visible Value
CLASS string true true cell
CONFIG.C_ALL_INPUTS string true true 0
CONFIG.C_ALL_INPUTS_2 string true true 0
CONFIG.C_ALL_OUTPUTS string true true 1
CONFIG.C_ALL_OUTPUTS_2 string true true 0
CONFIG.C_BASEADDR string true true 0x41200000
CONFIG.C_DOUT_DEFAULT string true true 0x00000000
CONFIG.C_DOUT_DEFAULT_2 string true true 0x00000000
CONFIG.C_FAMILY string true true zynq
CONFIG.C_GPIO2_WIDTH string true true 32
CONFIG.C_GPIO_WIDTH string true true 4
CONFIG.C_HIGHADDR string true true 0x4120FFFF
CONFIG.C_INTERRUPT_PRESENT string true true 0
CONFIG.C_IS_DUAL string true true 0
CONFIG.C_S_AXI_ADDR_WIDTH string true true 9
CONFIG.C_S_AXI_DATA_WIDTH string true true 32
CONFIG.C_TRI_DEFAULT string true true 0xFFFFFFFF
CONFIG.C_TRI_DEFAULT_2 string true true 0xFFFFFFFF
CONFIG.Component_Name string true true base_zynq_design_axi_gpio_0_0
CONFIG.EDK_IPTYPE string true true PERIPHERAL
CONFIG.GPIO2_BOARD_INTERFACE string true true Custom
CONFIG.GPIO_BOARD_INTERFACE string true true leds_4bits
CONFIG.USE_BOARD_FLOW string true true true
CONFIGURABLE bool true true 0
IP_NAME string true true axi_gpio
IP_TYPE enum true true PERIPHERAL
NAME string* true true axi_gpio_0
PRODUCT_GUIDE string true true AXI GPIO LogiCORE IP Product Guide (PG144)
SLAVES string true true  
VLNV string true true xilinx.com:ip:axi_gpio:2.0
# Memory range of the Slave IPs
common::report_property [lindex [hsi::get_mem_ranges -of_objects
[hsi::get_cells -filter {IP_TYPE==PROCESSOR}]] 39]
Table 4. Example Table
Property Type Read-only Visible Value
BASE_NAME string true true C_BASEADDR
BASE_VALUE string true true 0x41200000
CLASS string true true mem_range
HIGH_NAME string true true C_HIGHADDR
HIGH_VALUE string true true 0x4120FFFF
INSTANCE cell true true axi_gpio_0
IS_DATA bool true true 1
IS_INSTRUCTION bool true true 0
MEM_TYPE enum true true REGISTER
NAME string true true axi_gpio_0