Programmable LPDDR4 SI570 Clock2

VMK180 Evaluation Board User Guide (UG1411)

Document ID
UG1411
Release Date
2024-09-13
Revision
1.3 English

[Figure 1, callout 37]

The VMK180 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator (U3) connected to the GC inputs of U1 LPDDR4_2 interface bank 705. The LPDDR4_CLK2_P and LPDDR4_CLK2_N series capacitor coupled clock signals are connected to XCVM1802 device U1 pins AW27 and AY27, respectively. At power-up, this clock defaults to an output frequency of 200.000 MHz. User applications or the System Controller can change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the VMK180 board reverts this user clock to the default frequency of 200.000 MHz.

  • Programmable oscillator: Silicon Labs SI570BAB000299DG (10 MHz-945 MHz range, 200.000 MHz default)
  • I2C address 0x60
  • LVDS differential output, total stability: 61.5 ppm