[Figure 1, callout 20]
The HSPC connector J53 implements a subset of the full FMCP connectivity:
- 68 single-ended or 34 differential user-defined pairs (34 LA pairs: LA[00:33])
- 12 transceiver differential pairs
- 3 transceiver differential clocks
- 2 differential clocks
- 1 differential (REFCLK) clock C2M pair
- 1 differential (SYNC) clock C2M pair
- 239 ground and 15 power connections
See the FPGA Mezzanine Card (FMC) VITA 57.4 specification for additional information on the FMCP HSPC connector. The detailed Versal adaptive SoC connections for the feature described in this section are documented in the VMK180 board XDC file, referenced in Xilinx Design Constraints.