PMC MIO[13:25] Bank 500: USB 2.0 ULPI PHY

VMK180 Evaluation Board User Guide (UG1411)

Document ID
UG1411
Release Date
2024-09-13
Revision
1.3 English

The VMK180 board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI transceiver (U99) to support a USB 2.0 type-A connector (J308). A USB cable is supplied in the VMK180 evaluation kit (standard-A connector to host computer, USB 2.0 A connector to VMK180 board connector J308). The USB3320 is a high-speed USB 2.0 PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard defines the interface between the USB controller IP and the PHY device, which drives the physical USB bus. Using the ULPI standard reduces the interface pin count between the USB controller IP and the PHY device.

The USB3320 is clocked by a 24 MHz crystal (X8). See the Standard Microsystems Corporation (SMSC) USB3320 data sheet for clocking mode details. The interface to the USB3320 PHY is implemented through the IP in the XCVM1802 device PS.

The USB3320 ULPI transceiver circuit has a Micrel MIC2544 high-side programmable current limit switch (U100). This switch has an open-drain output fault flag on pin 2, which turns on red LED DS37 if over current or thermal shutdown conditions are detected. DS37 is located just above the U125 system controller component (callout 48 in the figure in Board Component Location).

Note: As shown in the following figure, the shield for the USB 2.0 type-A connector (J308) can be tied to GND by a jumper on header J300 pins 1-2 (default). The USB shield can optionally be connected through a series capacitor to GND by installing a capacitor (body size 0402) at location C2762 and jumping pins 2-3 on header J300.
Figure 1. USB3320 USB2.0 Connector J308 Shield Connection Options

The detailed adaptive SoC connections for the feature described in this section are documented in the VMK180 board XDC file, referenced in Xilinx Design Constraints.