[Figure 1, callout 5]
The VMK180 U1 XCVM1802 bank 500 PMC_MIO[0:12] pins are connected to the 240-pin (8 x 30) MIO connector J212. This interface enables high-speed XCVM1802 configuration using the X-EBM-01 QSPI external daughter card installed on J212.
The detailed adaptive SoC connections for the feature described in this section are documented in the VMK180 board XDC file, referenced in Xilinx Design Constraints. The XCVM1802 MIO connector J212 pinout is listed in the following figure.
Figure 1. MIO Connector J212 Pinout
