Traditional Design Flow for Embedded Systems - 2024.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2024-05-30
Version
2024.1 English

You can also use the traditional design flow to create designs with both PL and embedded software components. In this case, the flow is similar to the embedded software design flow used for AMD Zynq™ UltraScale+™ MPSoCs. The hardware team is responsible for creating, verifying, and implementing a hardware design that is used by the software team to develop the embedded software application.

Note: All recommendations for the traditional design flow for hardware-only systems apply to the traditional design flow for embedded systems.

Following are the main steps in this flow:

  1. Create and verify the hardware design using the Vivado IP integrator.
  2. Implement the hardware design using the Vivado implementation tools.
  3. Export the hardware design to the Vitis embedded software development flow.
  4. Develop the software application on top of the fixed hardware design using the Vitis embedded software development flow.
Note: The Vivado IP integrator is supported in Project Mode only.
Important: This design flow does not support programming of the AI Engine cores and is therefore only suitable for Versal Prime, Versal Premium, and Versal HBM devices which do not have AI Engine.