The configurable logic blocks (CLBs) in Versal adaptive SoCs differ from those in UltraScale devices. Vivado synthesis handles the architectural differences, but you must be aware of the differences noted in the following sections.
Carry Chains
Instead of the CARRY8 primitive in UltraScale devices, Versal adaptive SoCs include a LOOKAHEAD8 primitive. The LOOKAHEAD8 primitive does not include MUXCYs and XORCYs for arithmetic operations. Inferring these operators is necessary, which slightly increases the LUT count.
MUXFx Primitives
Versal adaptive SoCs do not include MUXFx primitives. Using MUXFx primitives for address decoding in distributed RAMs, large comparators, or MUX chains typically increases LUT counts in Versal adaptive SoCs. See the following figure.