If your previous design used soft memory controller IP, you have two choices. Use the Versal adaptive SoC soft memory controller IP or the integrated DDR memory controller. AMD recommends using the integrated DDR memory controller rather than using the Versal adaptive SoC soft memory controller IP.
In Versal adaptive SoC, you can use the integrated DDR memory controller only via the NoC. The NoC and DDR memory controller have very high bandwidth but generally have a higher latency than a standalone soft memory controller. The integrated DDR memory controller supports some I/O banks. For more information on the DDR memory controller, refer to the Versal Architecture and Product Data Sheet: Overview (DS950).
If you are using the soft memory controller IP, you must regenerate the IP for Versal adaptive SoC. In Versal adaptive SoC, an I/O bank comprises nine nibbles, and each nibble has six pins. Depending on the device and package, the integrated DDR memory controller dedicates specific I/O banks or nibbles within an I/O bank.
Soft memory controllers cannot use these dedicated pins. The package file marks pins dedicated to the integrated DDR memory controller as YES in the DDR memory controller ONLY column. The soft memory controllers can only use pins designated as NO.
For more information on soft memory controller IP, including detailed information on pinout, refer to the following guides:
- Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)
- Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)
- Versal Adaptive SoC Soft RLDRAM 3 Memory Controller LogiCORE IP Product Guide (PG354)
- Versal Adaptive SoC Soft QDR-IV SRAM Memory Controller LogiCORE IP Product Guide (PG355)