Logic Simulation Using SystemC Models - 2024.1 English

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2024-05-30
Version
2024.1 English

SystemC is a C++ library that enables hardware modeling. This library provides structural elements, such as modules, ports, and interfaces, as well as data types. In addition to cycle-accurate simulation models, AMD provides fast, transaction-accurate, SystemC simulation models for some Versal adaptive SoC infrastructure blocks for use in Vitis hardware emulation flows. SystemC models allow faster simulation compared to RTL models, which helps to reduce overall simulation time.

In general, SystemC models are used for performance analysis, architecture exploration, DMA synchronization, and address trace generation and performance modeling. However, AMD recommends using RTL models when accuracy and debugging are more important, such as with DMA transaction or timing dependent issues.